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AT26DF161
Figure 2-1.
8-SOIC Top View
CS
SO
WP
GND
1
2
3
4
8
7
6
5
VCC
NC
SCK
SI
3. Block Diagram
CONTROL AND
I/O BUFFERS
CS
SCK
INTERFACE
PROTECTION LOGIC
AND LATCHES
SRAM
DATA BUFFER
SI
SO
CONTROL
AND
LOGIC
Y-DECODER
Y-GATING
FLASH
WP
X-DECODER
MEMORY
ARRAY
4. Memory Array
To provide the greatest flexibility, the memory array of the AT26DF161 can be erased in four lev-
els of granularity including a full chip erase. In addition, the array has been divided into physical
sectors of uniform size, of which each sector can be individually protected from program and
erase operations. The size of the physical sectors is optimized for both code and data storage
applications, allowing both code and data segments to reside in their own isolated
regions. Figure 4-1 on page 4 illustrates the breakdown of each erase level as well as the break-
down of each physical sector.
3
3599H–DFLASH–8/09
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